1. Field of the Invention
The present invention relates to a plasma display panel (PDP) and a driving method thereof.
2. Discussion of the Related Art
The PDP is in the spotlight as a display device having many desirable characteristics because it has higher resolution, a higher rate of emission efficiency, and a wider view angle in comparison to other flat panel displays.
The PDP is a flat panel display for showing characters or images using plasma generated by gas discharge, and includes more than hundreds of thousands to millions of pixels arranged in a matrix format, in which the number of pixels are determined by the size of the PDP. A configuration of the PDP will now be described with reference to FIG. 1 and FIG. 2.
FIG. 1 shows a partial perspective view of the PDP, and FIG. 2 shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP has two glass substrates 1 and 6 that face each other with a gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on the first glass substrate 1, and the scan electrodes 4 and the sustain electrodes 5 are covered with a dielectric layer 2 and a protection film 3. A plurality of address electrodes 8 are formed on the second glass substrate 6, and the address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulator layer 7 between the address electrodes 8, and phosphors 10 are formed on the surface of the insulator layer 7 and on both sides of the barrier ribs 9. The glass substrates 1 and 6 are provided facing each other with discharge spaces 11 between the glass substrates 1 and 6 so that the scan electrodes 4 and the sustain electrodes 5 can cross the address electrodes 8. A discharge space 11 between the address electrode 8 and a crossing part of a pair of the scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.
As shown in FIG. 2, the electrodes of the PDP have an m×n matrix format. The address electrodes A1 to Am are arranged in the column direction, and n scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are arranged in the row direction.
Conventionally, a frame is divided into a plurality of subfields in order to operate the PDP, and gray scales are represented by a combination of the subfields. Each of the subfields includes a reset period, an address period, and a sustain period.
In the reset period, wall charges formed by previous sustain-discharging are eliminated, and the wall charges are established in order to perform the next address-discharging stably. In the address period, cells that are turned on and the cells that are turned off on the panel are selected, and the wall charges are accumulated to the cells that are turned on (i.e., addressed cells). In the sustain period, a discharge for substantially displaying images on the addressed cells is performed.
The term “wall charges” as used herein refers to charges that are formed on a wall of discharge cells neighboring each electrode and accumulated to electrodes. Although the wall charges do not actually touch the electrodes, it will be described that the wall charges are “generated”, “formed”, or “accumulated” thereon. Also, a wall voltage represents a potential difference formed on the wall of the discharge cells by the wall charges.
FIG. 3 shows a conventional PDP driving waveform diagram.
As shown in FIG. 3, a voltage at the scan electrode (i.e., Y electrode) is reduced to a voltage of VscL while a wall voltage between the scan electrode and the sustain electrode is maintained at a voltage which approximates a discharge firing voltage when the reset period is about to end. In the address period, a scan pulse which has the voltage of VscL as a low peak voltage and a voltage of VscH as a high peak voltage is applied to the scan electrode in sequence, and at the same time a data pulse is applied to the address electrode so as to generate an address discharge.
The address discharge is determined by the density of priming particles and the wall voltage generated in the discharge space. For the scan electrodes on the upper part of the panel, the address discharge is easily generated because the address discharge is generated only a short time after the reset period is finished, and therefore erroneous discharge may be generated when an excessive wall voltage is generated. On the contrary, in the scan electrodes on the lower part of the panel, it takes longer to apply the scan pulse after the reset discharge is generated, and therefore a voltage in the discharge space is gradually reduced because the density of the priming particles is reduced and the wall voltage is eliminated little by little. Accordingly, it takes longer to be discharged on the lower part of the panel than on the upper part of the panel and an address margin is problematically reduced.